Inspection method and inspection apparatus for semiconductor substrate

ABSTRACT

An inspection method for a semiconductor substrate includes irradiating an inspection beam on wires formed on a semiconductor substrate, detecting a secondary beam emitted from the semiconductor substrate, generating a contrast image, which indicates a state of an inspection surface of the semiconductor substrate, according to a gray level corresponding to signal intensity of the secondary beam, specifying a wire as an inspection target and a wire as a non-inspection target and acquiring a position and a dimension of the wire as the non-inspection target and a gray level corresponding to a wire non-forming area, replacing an image of the wire as the non-inspection target in the contrast image with an image having the gray level corresponding to the wire non-forming area, and inspecting, based on the contrast image after the replacement processing, a defect of the wire as the inspection target.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2009-051046, filed on Mar. 4,2009; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an inspection method and an inspectionapparatus for a semiconductor substrate, and, more particularly to aninspection method and an inspection apparatus of electric short-circuitand open-circuit in a semiconductor substrate.

2. Description of the Related Art

In a defect inspection in a hole forming process in manufacturing of asemiconductor device, a defect inspection method for acquiring apotential contrast image on a wire surface present in specific one chipon a wafer surface and comparing potential contrast images on the samewire surface between cells or dies adjacent to each other to detect adefect of wires is used (e.g., Japan Society for the Promotion ofScience, the 132nd Committee, 24th LSI Testing Symposium/2004 “LineMonitoring Method by Potential Contrast Defect Detection p 77-83”,Microlithography. Proceedings of SPIE vol. 5752 (2004) pp.997-1008/Development of voltage contrast inspection technique for linemonitoring 300 mm ULSI hp90 logic contact layer).

In general, such a defect inspection system is referred to ascell-to-cell image comparison inspection system or die-to-die imagecomparison inspection system depending on whether image comparison isperformed between cells or between dies. For example, a defectinspection apparatus for inspecting a defect using an electron beamrepresented by a product of KLA-Tencor Corporation adopts this system(concerning an inspection apparatus for inspecting a defect in asemiconductor device using an electron beam, see, for example, U.S. Pat.No. 6,768,324). The cell-to-cell image comparison inspection system isused when dies in which repetition wiring is present as in a memorydevice are inspected. The die-to-die image comparison inspection systemis used when dies in which repetition wires are not present as in alogic device are inspected.

In an inspection method for irradiating an electron beam on the surfaceof a semiconductor substrate, creating potential contrast images on thewire surface, and detecting critical defects (open circuit and shortcircuit) present in a layer under wires from a difference image of thepotential contrast images, when there are various wires in a device,fluctuation occurs in contrast in each of the wires. As a result, it islikely that deterioration in inspection accuracy is caused.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, an inspection methodfor a semiconductor substrate includes irradiating an inspection beam onwires formed on a semiconductor substrate while scanning the inspectionbeam, detecting a secondary beam emitted from the semiconductorsubstrate according to the irradiation of the inspection beam,generating a contrast image, which indicates a state of an inspectionsurface of the semiconductor substrate, according to a gray levelcorresponding to signal intensity of the secondary beam, specifying,based on a change in the gray level in the contrast image, a wire as aninspection target and a wire as a non-inspection target and acquiring aposition and a dimension of the wire as the non-inspection target and agray level corresponding to a wire non-forming area, replacing, based onthe position and the dimension of the wire as the non-inspection target,an image of the wire as the non-inspection target in the contrast imagewith an image having the gray level corresponding to the wirenon-forming area; and inspecting, based on the contrast image after thereplacement processing, a defect of the wire as the inspection target.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a configuration of an inspection apparatusfor a semiconductor substrate according to a first embodiment of thepresent invention;

FIG. 2 is a plan view of an example of a semiconductor substrate as aninspection target;

FIG. 3 is a diagram of an example of a waveform of a gray level acquiredfrom a potential contrast image;

FIG. 4 is a diagram of a potential contrast image obtained by replacingimages of trench wires with self-generated images;

FIG. 5 is a diagram of an example of a two-dimensional histogram used ina substrate inspection method according to the first embodiment;

FIG. 6 is a diagram of a difference in contrast in comparison of anon-defective image (a) and a defective image (b);

FIG. 7 is a diagram for explaining an image comparison system accordingto the first embodiment;

FIG. 8 is a flowchart of defect inspection according to the firstembodiment;

FIG. 9 is a plan view of another example of the semiconductor substrateas the inspection target;

FIG. 10 is a diagram of an example of a waveform of a gray levelacquired from a contrast image;

FIG. 11 is a diagram of a contrast image (an optical microscope image)obtained by replacing images of cell section end wires withself-generated images;

FIG. 12 is a flowchart of defect inspection according to a secondembodiment of the present invention; and

FIG. 13 is a block diagram of a configuration of an inspection apparatusfor a semiconductor substrate according to the second embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention are explained in detailbelow with reference to the accompanying drawings. The present inventionis not limited by the embodiments.

FIG. 1 is a block diagram of a configuration of an inspection apparatusfor a semiconductor substrate according to a first embodiment of thepresent invention. As shown in FIG. 1, the inspection apparatusaccording to this embodiment includes a filament electrode 1, asuppressor electrode 2, an extractor electrode 3, a capacitor lens 4, aWien filter (upper) 5, an aperture 6, a beam scanning deflector 7, aWien filter (lower) 8, an object lens 9, a top electrode (ground (GND)potential) 10, an intermediate electrode 11, a focus control electrode12, a substrate stage 15, a secondary electron detector 17, a signalprocessing device 18, a control computer 19, a display device 20, and aDC power supply 21. A semiconductor substrate 14 is mounted on thesubstrate stage 15. Negative voltage is applied to the substrate stage15 by a DC power supply 22.

The filament electrode 1 is an electron source that generates anelectron beam. The suppressor electrode 2, the extractor electrode 3,the capacitor lens 4, the Wien filter (upper) 5, the aperture 6, thebeam scanning deflector 7, the Wien filter (lower) 8, the object lens 9,the top electrode (GND potential) 10, the intermediate electrode 11, andthe focus control electrode 12 configure an electron optical system. Theelectron optical system controls the size, the track, the focusposition, and the like of a beam bundle of a primary electron beam 13irradiated on the semiconductor substrate 14. The primary electron beam13 is focused to form an image on the surface of the semiconductorsubstrate 14 by the electron optical system. The focused primaryelectron beam 13 is scanned on the semiconductor substrate 14 by thebeam scanning deflector 7. The filament electrode 1 and the electronoptical system configure an irradiating unit 50.

The DC power supply 21 applies DC voltage to the focus control electrode12 to control the focus of the primary electron beam 13. A secondaryelectron 16 as a secondary beam is emitted from the wire surface of thesemiconductor substrate 14 by the irradiation of the primary electronbeam 13. The secondary electron 16 is accelerated by an electric fieldformed between the semiconductor substrate 14 and the object lens 9 andmade incident on the Wien filter 8. Then the secondary electron 16 isdeflected by the Wien filter 8 and drawn into the second electrodetector 17.

The secondary electron detector 17 detects the secondary electron 16 andoutputs a signal corresponding to signal intensity (a detection amount)of the secondary electron 16. The signal processing device 18 convertsthe output of the secondary electron detector 17 into an image signal.The image signal is referred to as potential contrast image because theimage signal has contrast corresponding to a potential distribution onan inspection surface of the semiconductor substrate 14. The imagesignal is represented by a gray level. Such a contrast is caused bydifferences of structures, materials, and the like of components in thesemiconductor substrate 14.

The image signal generated by the signal processing device 18 is outputto the control computer 19 as a control processing unit. As explainedlater, the control computer 19 replaces images of wires as noise sourcesof inspection in the image signal with self-generated images anddetermines, based on the image signal after this replacement processing,acceptability of wires as inspection targets. The display device 20(e.g., a CRT) displays an inspection result together with images such asthe potential contrast image.

FIG. 2 is a plan view of an example of the semiconductor substrate 14 asan inspection target. As shown in FIG. 2, on the semiconductor substrate14, the same layout patterns are repeatedly formed in order of a trenchwire 24, an oxide film 25, a contact wire 26, and the oxide film 25 in adirection orthogonal to an extending direction of a trench wire 24 and acontact wire 26 (in FIG. 2, only a part of the layout patterns isshown). Specifically, a part of a memory cell area of a NAND memory anda part of wires thereof are shown. The contact wires 26 are contacts ona bit side and the trench wires 24 are contacts on a source side.

In FIG. 2, a defect candidate 27 of the contact wires 26 is shown. As itis seen from comparison with other sections of the contact wires 26, inthe defect candidate 27, contrast is bright, whereas the contrast shouldoriginally be dark in a non-defective. FIG. 6 is an enlarged diagram ofthe contrast in the contact wires 26. Whereas bright contrast appears ina defective image (b), dark contrast appears in a corresponding sectionof a non-defective image (a). In the following explanation, the contactwires 26 are inspection targets (wires as inspection targets) and thetrench wires 24 are wires that are not inspection targets (wires asnon-inspection targets). The oxide films 25 form areas in which wiresare not formed (wire non-forming areas).

The semiconductor substrate 14 is set on the substrate stage 15. When anelectron beam (e.g., incident voltage=1000 eV, probe current=75 nA, andcharge control voltage =−10 V) is irradiated on the surface of thesemiconductor substrate 14, a potential contrast image as an imagehaving contrast that depends on a potential distribution of thesemiconductor substrate 14 is output from the signal processing device18.

When the potential contrast image is acquired from the signal processingdevice 18, the control computer 19 acquires, for example, a waveform ofa gray level along a straight line L1 shown in FIG. 2 from the potentialcontrast image. FIG. 3 is a diagram of an example of the waveform of thegray level acquired from the potential contrast image and, specifically,a waveform along the straight line L1. In FIG. 3, a position coordinate(indicated in pixel units) as a wire position coordinate along thestraight line L1 is set as the abscissa and the gray level is set as theordinate. The gray level is digitized and indicated in, for example, 256gradations. A value of the gray level increases in order of a gray levelC1 of the trench wires 24, a gray level C2 of the contact wires 26, anda gray level C3 of the oxide films 25. Brighter contrast is obtained inthis order.

The control computer 19 calculates position coordinates 31-1 and 31-2 ofthe trench wires 24 and a dimension 29 of the trench wires 24 from thewaveform shown in FIG. 3 and specifies image areas of the trench wires24 in the potential contrast image. Further, the control computer 19calculates the gray level C3 of the oxide films 25 from the waveformshown in FIG. 3. In calculating the gray level C3, the control computer19 can calculate, for example, an average on the oxide films 25 or canobtain a value at specific one point. The dimension 29 of the trenchwires 24 in FIG. 3 is specifically width. When information concerningthe length of the trench wires 24 is necessary, the control computer 19acquires the information from the potential contrast image.

Subsequently, the control computer 19 creates self-generated images forreplacing images of the trench wires 24. The self-generated images areimages with a gray level thereof set to the gray level C3 of the oxidefilms 25. In this embodiment, defect inspection is performed after theimages of the trench wires 24 as noise sources in the potential contrastimage are replaced with the self-generated images to eliminate noise.

FIG. 4 is a diagram of a potential contrast image obtained by replacingthe images of the trench wires 24 with self-generated images 28. In FIG.4, the wires (the trench wires 24) as noise sources are replaced withthe self-generated images 28. The self-generated images 28 are generatedin size obtained by adding a slight margin to the image areas of thetrench wires 24. However, the size can be arbitrarily set as long as theself-generated images 28 include the image areas of the trench wires 24and do not overlap image areas of the contact wires 26.

As explained above, a difference occurs in a gray level (signalintensity) in a non-defective product and a defective product betweencorresponding sections in the contrast image.

Therefore, after the noise sources are eliminated as shown in FIG. 4,cell-to-cell image comparison or die-to-die image comparison is carriedout, and presence or absence of a defect can be determined based on avalue of the difference in the gray level.

FIG. 5 is a diagram of an example of a two-dimensional histogram used ina substrate inspection method according to this embodiment. In FIG. 5,the abscissa represents the luminance (gradation) of a reference imageand the ordinate represents the luminance (gradation) of a comparisonimage that is compared with the reference image. As an example, imagecomparison of a cell A (the reference image) and a cell B (thecomparison image) is performed (the cell-to-cell image comparisonsystem). First, the potential contrast image shown in FIG. 4 is createdfor each of the cells A and B. The two-dimensional histogram shown inFIG. 5 is created for the cells. Specifically, a gray level α ofarbitrary one pixel in the cell A is taken as a value on the abscissa, agray level β of a pixel in the cell B present in a positioncorresponding to the arbitrary pixel is taken as a value on theordinate, and (α,β) is plotted. A set of points shown in FIG. 5. isobtained by plotting (α,β) for all pixels in the cells A and B.

When both the cells A and B are non-defective, α and β are substantiallythe same gradations. However, one of the cells A and B is defective, adeviation between α and β increases. Therefore, reference values(thresholds) for determination of a defect are set based on adistribution of the set of points shown in FIG. 5. Acceptability can bedetermined by comparing (α,β) with the thresholds. In the example shownin the figure, the thresholds are set by, for example, straight lines T1and T2 passing through the origin of 0 gradation. Points located betweenthe straight lines T1 and T2 are determined as non-defective (normal)and the other points are determined as defective (defects). For example,concerning a point P1, α=30 and β=120. This indicates that the cells Aand B respectively correspond to dark contrast (gradation 30) in thenon-defective image (a) shown in FIG. 6 and bright contrast (gradation120) in the defective image (b) shown in FIG. 6 and a defect is presentin the contact wires 26 in the cell B.

FIG. 7 is a diagram for explaining an image comparison system accordingto this embodiment. In FIG. 7, an example of image comparison concerningthe adjacent cells A and B on the semiconductor substrate 14 is shown.The cell A is non-defective and the cell B is defective. A wafer stagecoordinate in a defect section in the cell B is, for example, (X,Y)=(+100 mm, +200 mm). The wafer stage coordinate of the defect sectionor a coordinate described as a defect position coordinate in FIG. 7 is acoordinate indicating an arrangement position of a cell, for example, aposition coordinate of the center of the cell. The wafer stagecoordinate is an X-Y coordinate set on a wafer. In the example shown inthe figure, X and Y are set in a range of 0 millimeter to 300millimeters.

In this embodiment, the potential contrast image with noise sourceseliminated shown in FIG. 4 is created for each of the cells A and B.Presence of a defect in the cell B can be determined by comparing theimage of the cell A and the image of the cell B as shown in FIG. 5. Thesame holds true for the die-to-die image comparison system. Defectinspection is performed by comparing areas of the same pattern indifferent dies.

FIG. 8 is a flowchart of defect inspection according to this embodiment.

First, the semiconductor substrate 14 as an inspection target is set onthe substrate stage 15 (S1). Subsequently, an electron beam conditioncorresponding to the structure of the semiconductor substrate 14 is set(S2). The semiconductor substrate 14 has, for example, wiring structureshown in FIG. 2. As the electron beam condition in this case is, asexplained above, for example, incident voltage=1000 eV, probe current=75nA, and charge control voltage=−10 V. Designation of an inspectiontarget area is performed by selecting a place where wires are arrangedperiodically for a certain range in an arbitrary chip and causing thecontrol computer 19 to store an area including the trench wires 24, theoxide films 25, and the contact wires 26 on the semiconductor substrate14.

Subsequently, after a recipe including information necessary for defectinspection is selected in the control computer 19, wafer alignment iscarried out. After the wafer alignment ends, inspection is started.First, the primary electron beam 13 is scanned on the semiconductorsubstrate 14 as the inspection target while moving the substrate stage15 (S3) and a potential contrast image of the wire surface of thesemiconductor substrate 14 is acquired (S4).

The control computer 19 acquires waveforms of the trench wires 24, theoxide films 25, and the contact wires 26 from the acquired potentialcontrast image (S5 in FIG. 3). The control computer 19 calculates thedimension 29 of the trench wires 24, the position coordinates 31-1 and31-2 of the trench wires 24, and signal intensity (the gray level C3) ofthe oxide films 25 from the acquired waveforms (S6). The controlcomputer 19 creates the self-generated images 28 shown in FIG. 4 fromthese kinds of information (S7). The control computer 19 replaces imagesof the trench wires 24 as noise sources with the self-generated images28 (S8). In this way, the control computer 19 eliminates noise byreplacing the images of the trench wires 24 as the noise sources withthe self-generated images 28.

The control computer 19 creates a two-dimensional histogram concerningsignal intensity of two images, for example, a reference image and acomparison image as cell images adjacent to each other (S9 in FIG. 5).In the two-dimensional histogram, the control computer 19 sets referencevalues (thresholds) for determining a defect (S10). This makes itpossible to determine whether a defect of electric short-circuit oropen-circuit is present in the contact wires 26. When it is determinedthat the defect is present, the control computer 19 extracts a positioncoordinate of the contact wire 26 in which the defect is present (S11).The position coordinate is given as a wafer stage coordinate of a cellas explained above.

According to this embodiment, even when wires as non-inspection targets(e.g., the trench wires 24) as noise sources are present in defectinspection, images of the wires as the non-inspection targets arereplaced with the self-generated images 28 to eliminate the noisesources. Therefore, there is an effect that it is possible to highlyaccurately inspect whether a defect is present in wires as inspectiontargets (e.g., the contact wires 26).

Because the waveform of the gray level shown in FIG. 3 is acquired, thetrench wires 24, the oxide films 25, the contact wires 26 can bespecified from a change in the gray level. The positions and thedimension of the trench wires 24 and the gray level C3 of the oxidefilms 25 can be acquired. The self-generated images 28 can be easilycreated.

The two-dimensional histogram concerning luminance (gradations) of thereference image and the comparison image is created as shown in FIG. 5.Presence or absence of a defect is determined by setting the referencevalues (the thresholds) for determining a defect. Therefore, inspectionof a defect can be easily and highly accurately carried out.

This embodiment can be suitably applied when wires as inspection targetsand wires as non-inspection targets are regularly (periodically)arranged. In general, image comparison is performed cell to cell or dieto die. However, the image comparison is not limited to this. The imagecomparison can be applied to images in a pair of areas on thesemiconductor substrate 14 in which the same wiring patterns arerespectively formed. As a beam irradiated on the semiconductor substrate14, a beam of charged particles other than the electron beam can also beused.

The wires as the inspection targets, the wires as the non-inspectiontargets, and the wire non-forming areas in this embodiment are examplesonly. This embodiment can be applied to other examples as well.

In a second embodiment of the present invention, a light beam emittedfrom, for example, an optical laser or an optical lamp is used as aninspection beam. Specifically, the light beam is irradiated on asemiconductor substrate while being scanned. A contrast image is createdaccording to signal intensity of reflected light reflected from thesemiconductor substrate. After wire images as noise sources in thecontrast image is replaced with self-generated images, a defect of wiresas inspection targets is inspected by using the contrast image after thereplacement processing.

FIG. 13 is a block diagram of a configuration of an inspection apparatusfor a semiconductor substrate according to this embodiment. As shown inFIG. 13, an irradiating unit 60 according to this embodiment includes alaser beam source 61 as a source of generation of a laser beam, adeflecting device 62 that deflects and scans a laser beam 65 emitted bythe laser beam source 61, and an object lens 63 that converges the laserbeam 65 on the semiconductor substrate 14. A photodetector 64 detectsreflected light 66 as a secondary beam reflected from the semiconductorsubstrate 14 and outputs a signal corresponding to light intensity ofthe reflected light 66. In FIG. 13, only necessary minimum components ofthe irradiating unit 60 are shown and other components are not shown. InFIG. 13, components same as those shown in FIG. 1 are denoted by thesame reference numerals and detailed explanation of the components isomitted.

FIG. 9 is a plan view of another example of the semiconductor substrate14 as the inspection target. As shown in FIG. 9, on the semiconductorsubstrate 14, cell sections 45 and cell section end wires 35 arealternately formed repeatedly. In the cell sections 45, intra-cell wiresand intra-cell oxide films are respectively formed in predeterminedsections. In FIG. 9, specifically, a part of a memory cell area of aNAND memory and a part of wires of the memory cell area are shown. Thecell section end wires 35 indicate selected gate formation areas.

In FIG. 9, a defect candidate 50 of the intra-cell wires is shown. As itis seen from comparison with other sections in the cell sections 45, adefect section having dark contrast compared with the periphery ispresent in the defect candidate 50. In the following explanation, theintra-cell areas are inspection targets (wires as inspection targets),the cell section end wires 35 are wires that are not inspection targets(wires as non-inspection targets), and the intra-cell oxide films areareas in which wires are not formed (wire non-forming areas).

When the laser beam 65 is irradiated on the semiconductor substrate 14,a part of incident light is reflected by the semiconductor substrate 14.The photodetector 64 detects reflected light 66 having light intensitythat depends on a state (e.g., the thickness and the material of wires)of an inspection surface of the semiconductor substrate. The signalprocessing device 18 outputs, based on a detection signal of thephotodetector 64, a contrast image (an optical microscope image) as animage having contrast that depends on the intensity of the reflectedlight from the semiconductor substrate 14.

When the contrast image is acquired from the signal processing device18, the control computer 19 acquires, for example, a waveform of a graylevel along a straight line L4 shown in FIG. 9 from the contrast image.FIG. 10 is a diagram of an example of the waveform of the gray levelacquired from the contrast image and, specifically, a diagram of awaveform along the straight line L4. In FIG. 10, a position coordinate(indicated in pixel units) as a wire position coordinate along thestraight line L4 is set as the abscissa and the gray level is set as theordinate. The gray level is digitized and indicated in, for example, 256gradations.

A gray level of the intra-cell wires and the intra-cell oxide films inthe cell sections 45 is C4. On the other hand, a gray level of the cellsection end wires 35 is C5 (>C4). Areas having a gray level C6 lowerthan C4 are present on both the sides of the cell section end wires 35.

The control computer 19 calculates position coordinates 43-1, 43-2, and43-3 of the cell section end wires 35 and a dimension 39 of the cellsection end wires 35 from the waveform shown in FIG. 10 and specifiesimage areas of the cell section end wires 35 in the contrast image.Further, the control computer 19 calculates the gray level C4 from thewaveform shown in FIG. 10. C4 is a gray level determined based on atleast a gray level of the intra-cell oxide films and is, for example, anaverage of gray levels of the cell sections 45 (an average concerningthe intra-cell oxide films and the intra-cell wires). The dimension 39is specifically width. When information concerning the length of thecell section end wires 35 is necessary, the control computer 19 acquiresthe information from the contrast image. The dimension 39 includes areasup to low contrast areas (gradation C6) present on both the sides of thecell section end wires 35.

Subsequently, the control computer 19 creates self-generated images forreplacing images of the cell section end wires 35. The self-generatedimages are images with a gray level thereof set to the gray level C4 ofthe cell sections 45. In this embodiment, defect inspection is performedafter the images of the cell section end wires 35 as noise sources inthe contrast image are replaced with the self-generated images toeliminate noise.

FIG. 11 is a diagram of a contrast image (an optical microscope image)obtained by replacing the images of the cell section end wires 35 withself-generated images 36. In FIG. 11, the wires (the cell section endwires 35) as noise sources are replaced with the self-generated images36.

A difference occurs in a gray level (signal intensity) in anon-defective product and a defective product between correspondingsections in the contrast image. Therefore, after the noise sources areeliminated as shown in FIG. 11, cell-to-cell image comparison ordie-to-die image comparison is carried out. Presence or absence of adefect can be determined based on a value of the difference in the graylevel. An inspection method for inspecting a semiconductor substrateusing a two-dimensional histogram is the same as that in the firstembodiment (FIGS. 5 and 7). Therefore, explanation of the inspectionmethod is omitted.

FIG. 12 is a flowchart of defect inspection according to thisembodiment.

First, the semiconductor substrate 14 as an inspection target is set onthe substrate stage 15 (S21). Subsequently, an optical conditioncorresponding to the structure of the semiconductor substrate 14 is set(S22). Designation of an inspection target area is performed byselecting a place where wires are arranged periodically for a certainrange in an arbitrary chip and causing the control computer 19 to storean area including the cell sections 45 (the intra-cell wires and theintra-cell oxide films) and the cell section end wires 35 on thesemiconductor substrate 14.

Subsequently, after a recipe including information necessary for defectinspection is selected in the control computer 19, wafer alignment iscarried out. After the wafer alignment ends, inspection is started.First, a light beam (the laser beam 65) is scanned on the semiconductorsubstrate 14 as the inspection target while moving the substrate stage15 (S23) and a contrast image (an optical microscope image) havingcontrast that depends on the thickness, the material, and the like ofthe wires on the semiconductor substrate 14 is acquired (S24).

The control computer 19 acquires waveforms of the cell section end wires35, the intra-cell wires, and the intra-cell oxide films from theacquired contrast image (optical microscope image) (S25 in FIG. 10). Thecontrol computer 19 calculates the dimension 39 of the cell section endwires 35, the position coordinates 43-1, 43-2, and 43-3 of the cellsection end wires 35, and signal intensity (the gray level C4) of theintra-cell wires and the intra-cell oxide films from the acquiredwaveforms (S26). The control computer 19 creates the self-generatedimages 36 shown in FIG. 11 from these kinds of information (S27). Thecontrol computer 19 replaces images of the cell section end wires 35 asnoise sources with the self-generated images 36 (S28). In this way, thecontrol computer 19 eliminates noise by replacing the images of the cellsection end wires 35 as the noise sources with the self-generated image36.

The control computer 19 creates a two-dimensional histogram concerningsignal intensity of two images, for example, a reference image and acomparison image as cell images adjacent to each other (S29 in FIG. 5).In the two-dimensional histogram, the control computer 19 sets referencevalues (thresholds) for determining a defect (S30). This makes itpossible to determine whether a defect of electric short-circuit oropen-circuit is present in the intra-cell wires. When it is determinedthat the defect is present, the control computer 19 extracts a positioncoordinate of the intra-cell wire in which the defect is present (S31).

According to this embodiment, even when wires as non-inspection targetsas noise sources (e.g., the cell section end wires 35) are present indefect inspection, images of the wires as the non-inspection targets arereplaced with the self-generated images 36 to eliminate the noisesources. Therefore, there is an effect that it is possible to highlyaccurately inspect whether a defect is present in wires as inspectiontargets (e.g., the intra-cell wires). This embodiment can be suitablyapplied when wires as inspection targets and wires as non-inspectiontargets are regularly arranged. Other effects of this embodiment are thesame as those of the first embodiment.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. An inspection method for a semiconductor substrate comprising:irradiating an inspection beam on wires formed on a semiconductorsubstrate while scanning the inspection beam; detecting a secondary beamemitted from the semiconductor substrate according to the irradiation ofthe inspection beam; generating a contrast image, which indicates astate of an inspection surface of the semiconductor substrate, accordingto a gray level corresponding to signal intensity of the secondary beam;specifying, based on a change in the gray level in the contrast image, awire as an inspection target and a wire as a non-inspection target andacquiring a position and a dimension of the wire as the non-inspectiontarget and a gray level corresponding to a wire non-forming area;replacing, based on the position and the dimension of the wire as thenon-inspection target, an image of the wire as the non-inspection targetin the contrast image with an image having the gray level correspondingto the wire non-forming area; and inspecting, based on the contrastimage after the replacement processing, a defect of the wire as theinspection target.
 2. The inspection method for a semiconductorsubstrate according to claim 1, wherein contrast images after thereplacement processing are acquired for a pair of areas on thesemiconductor substrate in which same wiring patterns are formed,respectively, a two-dimensional histogram is created concerning a graylevel of each of pixels in one contrast image after the replacementprocessing and a gray level of each of pixels in the other contrastimage after the replacement processing, and a threshold for determininga non-defective product and a defective product is applied to thehistogram to inspect the defect of the wire as the inspection target. 3.The inspection method for a semiconductor substrate according to claim2, wherein the semiconductor substrate is mounted on a substrate stage,and when it is determined that a defect is present in the wire as theinspection target in one of the pair of areas, a position coordinate ofthe area indicated by a coordinate on the substrate stage is outputtedas a defect position.
 4. The inspection method for a semiconductorsubstrate according to claim 2, wherein both the pair of areas are cellsor dies.
 5. The inspection method for a semiconductor substrateaccording to claim 1, wherein a waveform of a gray level along onedirection including a gray level of the wire as the inspection target,the wire as the non-inspection target, and the wire non-forming area isacquired from the contrast image, and the position and the dimension ofthe wire as the non-inspection target and the gray level correspondingto the wire non-forming area is acquired from the waveform.
 6. Theinspection method for a semiconductor substrate according to claim 5,wherein the gray level corresponding to the wire non-forming area isgiven as an average of gray levels of the wire non-forming area in thewaveform.
 7. The inspection method for a semiconductor substrateaccording to claim 5, wherein the gray level corresponding to the wirenon-forming area is given as an average of gray levels of the wire asthe inspection target and the wire non-forming area in the waveform. 8.The inspection method for a semiconductor substrate according to claim1, wherein the wire as the inspection target and the wire as thenon-inspection target are regularly arranged.
 9. The inspection methodfor a semiconductor substrate according to claim 1, wherein theinspection beam is an electron beam.
 10. The inspection method for asemiconductor substrate according to claim 9, wherein the contrast imageis a potential contrast image having contrast corresponding to apotential distribution on the inspection surface of the semiconductorsubstrate.
 11. The inspection method for a semiconductor substrateaccording to claim 1, wherein the inspection beam is a light beam. 12.The inspection method for a semiconductor substrate according to claim1, wherein the wire as the inspection target is a contact wire, the wireas the non-inspection target is a trench wire, and the wire non-formingarea is an oxide film.
 13. The inspection method for a semiconductorsubstrate according to claim 1, wherein a memory cell area is formed onthe semiconductor substrate, and the wire as the inspection target is anintra-cell wire, the wire as the non-inspection target is a cell sectionend wire, and the wire non-forming area is an intra-cell oxide film. 14.An inspection apparatus for a semiconductor substrate comprising: anirradiating unit that irradiates an inspection beam on wires formed on asemiconductor substrate while scanning the inspection beam; asecondary-beam detecting unit that detects a secondary beam emitted fromthe semiconductor substrate according to the irradiation of theinspection beam; a signal processing unit that generates a contrastimage, which indicates a state of an inspection surface of thesemiconductor substrate, according to a gray level corresponding tosignal intensity of the secondary beam; and a control processing unitthat specifies, based on a change in the gray level in the contrastimage, a wire as an inspection target and a wire as a non-inspectiontarget, acquires a position and a dimension of the wire as thenon-inspection target and a gray level corresponding to a wirenon-forming area, replaces, based on the position and the dimension ofthe wire as the non-inspection target, an image of the wire as thenon-inspection target in the contrast image with an image having thegray level corresponding to the wire non-forming area, and inspects,based on the contrast image after the replacement processing, a defectof the wire as the inspection target.
 15. The inspection apparatus for asemiconductor substrate according to claim 14, wherein the controlprocessing unit acquires contrast images after the replacementprocessing for a pair of areas on the semiconductor substrate in whichsame wiring patterns are formed, respectively, creates a two-dimensionalhistogram concerning a gray level of each of pixels in one contrastimage after the replacement processing and a grey level of each ofpixels in the other contrast image after the replacement processing, andapplies a threshold for determining a non-defective and a defective tothe histogram to inspect the defect of the wire as the inspectiontarget.
 16. The inspection apparatus for a semiconductor substrateaccording to claim 15, wherein the semiconductor substrate is mounted ona substrate stage, and the control processing unit outputs, when it isdetermined that a defect is present in the wire as the inspection targetin one of the pair of areas, a position coordinate of the area indicatedby a coordinate on the substrate stage as a defect position.
 17. Theinspection apparatus for a semiconductor substrate according to claim14, wherein the control processing unit acquires, from the contrastimage, a waveform of a gray level along one direction including a graylevel of the wire as the inspection target, the wire as thenon-inspection target, and the wire non-forming area and acquires, fromthe waveform, the position and the dimension of the wire as thenon-inspection target and the gray level corresponding to the wirenon-forming area.
 18. The inspection apparatus for a semiconductorsubstrate according to claim 17, wherein the gray level corresponding tothe wire non-forming area is given as an average of gray levels of thewire non-forming area in the waveform.
 19. The inspection apparatus fora semiconductor substrate according to claim 17, wherein the gray levelcorresponding to the wire non-forming area is given as an average ofgray levels of the wire as the inspection target and the wirenon-forming area in the waveform.
 20. The inspection apparatus for asemiconductor substrate according to claim 14, wherein the inspectionbeam is an electron beam or a light beam.